Intel 18A Yields Up 7%–8% Monthly as 2H26 Customers Expected; Said to Push 18A CPUs Amid Shortages
  Intel’s turnaround appears to be gaining momentum. According to CNBC, Intel CEO Lip-Bu Tan said the company’s foundry business is making progress, with 18A process yields now improving by 7% to 8% per month, signaling advancement from earlier challenges.  More significantly, Tan said the improvements are beginning to attract customer interest, with Intel expecting commitments from multiple foundry customers in the second half of 2026, the report highlights. The remarks align with earlier comments from CFO David Zinsner, who said signals from external foundry customers would become “more concrete” in the second half of the year and into early 2027.  Intel Reportedly Pushes 18A CPUs Amid Supply Tightness  Recent CPU shortages have also brought renewed attention to Intel, which is reportedly promoting processors built on its 18A technology. According to Nikkei, sources say Intel is encouraging key PC partners across the U.S., China, and Taiwan to increase adoption of CPUs produced using the process, which only became available late last year.  Sources add that the company has prioritized supply of chips based on its older Intel 7 process for server and industrial applications. Intel’s push to promote its most advanced chips comes as it seeks to capitalize on the AI race and regain leadership in advanced chipmaking, the report adds.  14A Seen as Intel’s Next Push Against TSMC  Beyond 18A, according to CNBC, Tan said Intel’s next-generation 14A process could eventually compete with TSMC, adding that it is expected to arrive around the same time as TSMC’s comparable technology — a development he described as a “major, major breakthrough.” As noted by Wccftech, Tan said Intel expects risk production for its 14A technology in 2028, followed by volume production in 2029, placing its timeline alongside TSMC’s. He added that multiple customers are already engaging with Intel as the company has made its 0.5 PDK available.  EMIB Shows Early Customer Commitment as Substrate Prepayments Emerge  Another major technology highlighted by Lip-Bu Tan is EMIB, which he described as one of the most advanced chip packaging technologies. According to Wccftech, Tan said customer commitment has become evident, with some customers even prepaying for substrates to secure supply amid ongoing shortages.  Wccftech notes that EMIB was recently said to have reached 90% yields. By contrast, Commercial Times notes that TSMC’s CoWoS currently mass-produced 5.5-reticle-size version — the world’s largest today — has already achieved yields of 98%.
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Release time:2026-05-20 11:32 reading:328 Continue reading>>
NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond HBM
  As AI models continue to scale, HBM may struggle to meet future memory-capacity demands, prompting industry experts to view GPU-driven storage architectures as a potential next frontier. According to The Elec, NVIDIA and Amazon are reportedly advancing storage architectures that allow GPUs to directly control storage devices such as SSDs. NVIDIA is said to plan the introduction of GPU-Initiated Direct Storage Access (GIDS) starting with its Vera Rubin AI platform, a shift that could accelerate the emergence of high-bandwidth flash (HBF), the report notes.  Citing Song Ki-hwan, a professor in the Department of System Semiconductor Engineering at Yonsei University, the report explains that GIDS goes beyond existing GPU Direct Storage (GDS) architecture. Under GDS, CPUs issue data requests to storage devices before data is transferred to GPUs. GIDS advances this by allowing GPUs to access storage directly, bypassing CPUs and DRAM.  Both GIDS and GDS aim to overcome data-transfer bottlenecks tied to traditional von Neumann computing architectures. Microsoft and AMD are also said to be exploring similar approaches. The report, citing Song, adds that traditional data-transfer methods are inefficient because CPUs are structurally limited in thread processing, while GPUs can generate tens of thousands of parallel threads. Song also notes that GPU-HBM data transfer already accounts for roughly half of total system power, strengthening the case for HBF architectures that place ultra-fast NAND closer to GPUs to address future AI bottlenecks.  GIDS Could Accelerate HBF and Expand NAND’s Role in AI Memory  The emergence of GIDS could allow NAND storage to take on a larger role in AI memory systems while easing pressure on HBM capacity. As the report notes, this shift would require higher-performance NAND flash capable of keeping pace with GPU processing speeds. One proposed approach is high-bandwidth flash (HBF), which stacks NAND flash vertically in a structure similar to HBM and connects it using through-silicon vias (TSVs).  The report notes that NAND flash offers roughly 30 times higher bit density than DRAM, enabling far greater memory capacity in a similar footprint. According to Song, combining six HBF units with two HBM units could increase GPU memory capacity more than 16 times, from 192GB to 3,120GB, potentially supporting AI models with parameter sizes around 16 times larger than current architectures.  Still, NAND flash has endurance limits, typically supporting only around 100,000 write-and-erase cycles versus DRAM’s near-unlimited write capability. As a result, HBF is seen as better suited for storing AI model parameters, which remain largely unchanged during inference and function as read-only workloads.  Meanwhile, memory makers have also been exploring GPU-driven memory architectures. According to an Edaily report last year, sources said Samsung Electronics is actively researching next-generation high-performance Z-NAND. The company is also developing GIDS technology that would allow GPUs to directly access Z-NAND-based storage devices. If implemented, GPUs would be able to access Z-NAND devices without intermediaries, potentially shortening processing times for AI workloads.
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Release time:2026-05-20 11:20 reading:422 Continue reading>>
First Intel Wildcat Lake Laptops Near Launch; Reportedly Built on 18A, Taking Aim at Apple’s MacBook Neo
  The first laptops powered by Intel’s “Wildcat Lake” Core Series 300 processors for the entry-level PC segment are reportedly nearing launch. According to Wccftech, Intel Core Series 3 laptops could hit retail shelves as early as next week, with initial models including 14-inch and 16-inch designs from Honor and ASUS, while more OEMs are expected to follow.  Chinese media outlet Mydrivers notes that the Honor Notebook X14 2026 Combat Edition will be the first commercially available laptop based on Intel’s Wildcat Lake platform, featuring an Intel Core 5 320 processor. Another Wccftech report notes that the device comes with 16GB of LPDDR5X 7467 MT/s memory, double the capacity of Apple’s MacBook Neo, along with a 512GB SSD. By comparison, the Neo starts at 256GB of storage and tops out at 512GB.  Intel’s Wildcat Lake Targets AI PCs With Better Battery Life  The SoC package integrates two dies, with the primary die built on Intel’s 18A node, according to TechPowerUp. This die features a 6-core CPU configuration, NPU 5 delivering 40 TOPS of INT8 performance, and a GPU with up to two Xe3 cores. It also integrates the memory controller and cache pool. Meanwhile, Intel dedicates the second die to I/O functions, the report adds.  Wccftech notes that Intel’s Core Series 3 emphasizes AI capability and battery efficiency, marking the company’s first hybrid AI-ready Core Series processor. The report adds that the chips are designed for all-day battery life and everyday productivity, offering up to 2.1 times faster creation and productivity performance, up to 64% lower processor power consumption, and up to 2.7 times higher AI GPU performance compared with previous-generation Intel Core 7 150U processors.  Looking ahead, Wildcat Lake could see broader adoption across future devices. TechPowerUp reports that Google is likely to pair its rumored “Googlebook” laptops with Intel’s latest Core Series 300 “Wildcat Lake” processors. However, Intel is not expected to be the exclusive platform provider, with Qualcomm and MediaTek also said to be among Google’s partners.
Release time:2026-05-19 10:42 reading:364 Continue reading>>
YC Chem Reportedly First to Supply Glass Substrate Photoresists; Customer Eyes Year-End Mass Production
  South Korea’s YC Chem has reportedly become the first in the industry to supply photoresists for glass substrates. According to The Elec, sources say the company is supplying i-line photoresist, stripper, and developer materials for glass substrates to a customer after receiving a purchase order (PO) following qualification tests.  As supply of related materials begins to ramp up, commercialization of glass substrates also appears to be drawing closer, the report notes. Current shipments are intended for the customer’s prototype production, with material supply volumes expected to increase gradually as the customer moves toward mass production from the end of this year.  The company is also seeking additional customers. According to the report, it is currently in discussions with more than three companies regarding the supply of glass substrate materials. With some firms, sample testing is underway for negative photoresists and glass substrate coating materials.  YC Chem has also supplied prototype coating materials for glass substrates to customers. These materials are intended to minimize cracking and warpage caused by differences in thermal expansion coefficients (CTE) and thermal conductivity between glass and copper. According to the report, the products are currently undergoing qualification testing.  The report notes that the coating materials are used in embedding-type glass substrates, which integrate circuits and passive components directly within the glass substrate itself.  Key Requirements for Photoresists in Glass Substrate Manufacturing  As the report points out, the glass substrate photoresist supplied by YC Chem is based on i-line technology, which uses a 365-nanometer (nm) mercury lamp wavelength in the lithography process. Notably, the report points out that, unlike extreme ultraviolet (EUV) photoresists used in advanced semiconductor manufacturing, glass substrate production places greater emphasis on thicker film thickness and strong etch resistance.  In particular, the report states that through-glass via (TGV) processes require strong chemical durability and high etch resistance during hole formation and copper plating. As a result, demand is increasing for longer-wavelength lithography materials such as i-line and krypton fluoride (KrF)-based photoresists.  In South Korea, Samyang NC Chem is also developing photoresist materials for glass substrates. The report adds that the company has supplied samples to more than two customers and is reportedly aiming for mass production next year.  As major companies accelerate glass substrate development, securing stable material supplies is becoming increasingly important. A January Chosun Biz report said Absolics is diversifying suppliers by adding a domestic partner for glass substrate photoresists, reducing reliance on Japan’s TOK, while also reviewing process dualization for TGV and plating processes through additional collaborators.
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Release time:2026-05-18 13:05 reading:374 Continue reading>>
Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%
  Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.  The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.  More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.  The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.  Commercialization Timeline Remains Unclear  Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.  Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.  SK hynix Advances Mobile AI Packaging  SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.  Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.
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Release time:2026-05-15 10:49 reading:483 Continue reading>>
Visit NOVOSENSE at PCIM Europe 2026!
  We warmly invite you to visit NOVOSENSE at PCIM Europe 2026. Discover how NOVOSENSE empowers innovation across automotive electronics, renewable energy & power supply, and industrial control with a comprehensive portfolio of isolators, interfaces, drivers, sensors, signal chain, and power management ICs.  Date: June 9–11, 2026  Venue: Nuremberg Exhibition Centre, Germany  Booth: Hall 4A, Booth 119  ✦ What to Expect ✦  Functional safety ICs for safety-critical automotive systems  One-stop body control & automotive lighting solutions  SerDes and ultrasonic radar IC solutions for smarter mobility  Technical presentations on high-voltage electric mobility and AI data center power systems  ✦ Highlights Preview ✦  Functional Safety ICs for Safety-Critical Automotive Systems  Isolated gate driver NSI6911F — certified by TÜV Rheinland to meet ISO 26262 ASIL D requirements, featuring up to 19A peak drive capability, ±150kV/μs CMTI, an integrated 12-bit isolated ADC, and advanced diagnostic functions for high-voltage applications such as traction inverters, OBCs, and DC-DC converters.  ASIL B ultrasonic radar ASSP NSUC1800 and LED driver NSL21924FS , reflecting NOVOSENSE's expanding functional safety portfolio across sensors, signal chain, power management, and driver ICs.  One-Stop Automotive Body Control & Lighting Solutions  For BCM and ZCU applications, NOVOSENSE offers motor driver products for brushed DC motors, stepper motors, BLDC motors, relays, valves, and solenoids, supporting efficient, precise, and safe motor control.  For automotive lighting, NOVOSENSE will showcase full-scenario LED driver solutions for ambient lighting, reading lights, headlighting, rear lighting, ISD/ISC lighting, grille lighting, and more, helping create safer, smarter, and more distinctive vehicle lighting experiences.  Enabling Smarter Mobility with SerDes and Ultrasonic Radar IC Solutions  SerDes chipset — NLS9116 single-channel serializer and NLS9246 four-channel deserializer, designed for cameras, displays, and domain controllers in ADAS and intelligent cockpit systems.  AK2 ultrasonic radar ASSP — comprising the NSUC1800 sensor-side chip and NSUC1802 host-side interface conversion chip, providing a turnkey solution for applications such as UPA and APA.  ✦ Keynote Speeches ✦  Join NOVOSENSE experts at PCIM Europe 2026 for in-depth technical presentations on how advanced semiconductor technologies are addressing the evolving demands of high-voltage electric mobility and AI data center power systems.  E-Mobility & Energy Storage Stage  Hall 6, Booth 220  Topic: Evolution and Challenges of Gate Driver Technology for New Generation of xEV Powertrain System  Time: June 9, 2026 | 15:25–15:45 (GMT+1)  Speaker: Timmy Wu  Topic: Enabling EV High-Voltage Safety with Advanced Isolated Sensing  Time: June 11, 2026 | 12:05–12:25 (GMT+1)  Speaker: Lillian Liu  AI & Data Centers Stage  Hall 5, Booth 320  Topic: Power Density Scaling in AI Data Centers: From System Constraints to Semiconductor Device Challenges  Time: June 9, 2026 | 14:35–14:55 (GMT+1)  Speaker: Wenzhe Xu
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Release time:2026-05-14 11:40 reading:480 Continue reading>>
SMIC Founder Says China May Gain Edge in Niche Chips as 80% of Demand Lies Outside Advanced Nodes
  As China pushes to strengthen its chip industry, Richard Chang, founder of SMIC, China’s largest foundry, suggests that success in semiconductors is not solely about winning the 2nm or 3nm race, with niche markets potentially emerging as a key competitive advantage for China. According to STAR Market Daily, Chang said that niche markets have become a key breakthrough point for China’s semiconductor industry, adding that advancing in specialized market segments could help strengthen the country’s overall chip capabilities.  SMIC remains limited to the 7nm node due to its reliance on older DUV lithography equipment. However, Richard Chang’s emphasis on niche markets suggests that the company’s mature-node technologies could still find meaningful opportunities across a range of applications, as noted by Wccftech.  SMIC Founder Highlights Opportunity Beyond Advanced Nodes  As noted by STAR Market Daily, Richard Chang argued that semiconductor success should not be defined solely by achieving 3nm or 2nm nodes, describing such thinking as a misconception and highlighting niche markets as a key opportunity for China’s chip industry.  Chang further noted that advanced nodes account for less than 20% of the global semiconductor market by product volume, while more than 80% of demand comes from mature-node and specialty-process segments. According to Chang, many niche markets still dominated by overseas players could represent key breakthrough opportunities for Chinese semiconductor companies.  The trend may already be emerging across parts of the supply chain. According to TrendForce, with Taiwanese foundries shifting capacity and raising prices, customers in HV processes and CIS applications are increasingly turning to Chinese foundries for more stable pricing and capacity availability. This order migration has been evident since the second half of 2025, driving strong demand for 90 nm-and-above 12-inch wafers among Chinese players.  Beyond Large Models: Richard Chang Highlights Edge AI Potential  In addition, Richard Chang argued that edge AI and scenario-driven applications remain underappreciated opportunities within the broader AI landscape. As STAR Market Daily notes, Chang said sectors such as industrial control, automotive electronics, and wearable devices could create strong demand for application-specific semiconductor solutions, offering startups room to pursue differentiated strategies outside direct competition with global AI giants.
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Release time:2026-05-12 10:24 reading:416 Continue reading>>
ARM CEO Says Agentic AI May Drive CPU Core Counts to 512 as GPU-CPU Ratios Become Less Relevant
  The rise of agentic AI is fueling fresh debate over the future GPU-to-CPU balance in AI systems, with Arm CEO Rene Haas now weighing in on the discussion. According to a transcript published by Investing.com, Haas said that while CPUs may not outnumber GPUs on a chip basis, they could from a core-count perspective.  Haas noted that overall CPU demand is likely to increase significantly as agentic AI scales, with data centers potentially requiring more than four times today’s CPU capacity. He said this could create a data center CPU market opportunity exceeding US$100 billion by 2030.  At the same time, Haas emphasized that the industry is seeing not only an explosion in overall CPU demand, but also rapid growth in the number of cores per CPU. According to Haas, many agentic AI workloads involve independent jobs, flows, or batches running on dedicated CPU cores, increasing the need for higher-core-count processors.  Haas used Blackwell, Rubin, and other large AI accelerators as examples, noting that these chips are already approaching reticle limits, meaning their size is constrained by the maximum area a lithography mask can print. In contrast, he said CPU core counts could still double or even quadruple over the coming years.  Haas noted that the Arm AGI CPU already features 136 cores, significantly higher than many competing offerings. Looking ahead, he said the industry is likely to move toward 256-core and even 512-core CPU designs. He added that such high-core-count architectures play to Arm’s strengths, as efficiency per core becomes increasingly critical at larger scales.  Mydrivers notes that AMD and Intel are moving in a similar direction. AMD’s 2nm Zen 6-based EPYC processors are already expected to reach up to 256 cores with SMT multithreading support, while Intel’s all-E-core Xeon processors have reached 288 cores, with the next generation expected to scale to as many as 512 cores.  Regarding the Arm AGI CPU launched at the company’s Arm Everywhere event last quarter, Haas said customer response has been “very strong.” He added that customer demand across fiscal 2027 and fiscal 2028 has already exceeded US$2 billion, more than double the level projected at launch.
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Release time:2026-05-11 13:48 reading:423 Continue reading>>
Apple Reportedly Keeps 2nm 5G Modem Orders with TSMC Amid Intel Cooperation Signals
  While recent market chatter has focused on a potential shift by Apple between longtime foundry partner TSMC and Intel, the Economic Daily News, citing industry sources, reports that the Cupertino-based company remains heavily dependent on the Taiwanese foundry giant, as it plans to place its entire in-house 5G modem orders with TSMC, leveraging its 2nm process technology.  The report suggests that Apple’s self-developed 5G modem chips are expected to power future iPhone, iPad, and Apple Watch devices, replacing modems from Qualcomm. The volume used across its product lineup is projected to reach hundreds of millions of units, the report adds.  Notably, Apple’s iPhone 17 lineup is expected to be the last to ship with Qualcomm Incorporated’s 5G modems, as the company moves toward a full transition to its in-house C2 baseband chip across all iPhone 18 models, according to Wccftech.  The C2 development builds on Apple’s earlier in-house modem effort. Apple’s C1, first introduced in early 2025 with the iPhone 16e, marked its most complex chip system to date, integrating a 4nm baseband modem and a 7nm transceiver, according to earlier reporting from Reuters. The Economic Daily News further reports that Apple Inc.’s in-house C2 5G modem is expected to add full mmWave support—addressing the Sub-6 GHz limitation of its predecessor—while also incorporating satellite connectivity.  Supply chain sources cited in the Economic Daily News report say TSMC has already secured foundry orders for Apple’s modem chips. Its back-end testing partner is also reportedly preparing for higher demand, with around 600 test systems being procured, as capacity is set to ramp from 2027.  Apple’s Chip Tug-of-War: TSMC vs Intel  Though claims of an Apple order shift to Intel remain unconfirmed, and any such move would not signal a departure from TSMC, cooperation between Apple and Intel appears to be warming. According to The Wall Street Journal, the two companies have reportedly reached a preliminary agreement for Intel to manufacture some of the chips powering Apple devices.  The two sides have been engaged in intensive talks for more than a year, with a formal deal said to have been hammered out in recent months, the report adds.  In parallel, Commercial Times reported earlier that Apple is evaluating Intel’s 18A-P process for its M-series chips. Looking further ahead, The New 7 reports that the first Intel-manufactured low-end M-series chips could emerge as early as mid-2027 under contract production, likely targeting entry-level Macs or iPads.  As highlighted by The Wall Street Journal, Apple’s reported outreach to Intel may reflect growing supply chain pressures, as the Cupertino firm—long TSMC’s top customer—faces tightening access to advanced manufacturing capacity amid surging demand from NVIDIA and other AI chip designers.  Intel previously played a central role in powering Apple’s Mac lineup, before Apple transitioned in 2020 to its own Arm-based custom chips, the report points out.
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Release time:2026-05-11 11:12 reading:437 Continue reading>>
TSMC, Sony to Form JV for Image Sensors, Including New Production Lines for AI and Automotive Use
  As TSMC has decided to upgrade its 2nd Kumamoto fab to 3nm, the foundry giant is also exploring to secure more opportunities for its mature nodes in Japan. According to its press release on May 8, Sony and TSMC announced the signing of a non-binding memorandum of understanding (MOU) to establish a strategic partnership focused on the development and manufacturing of next-generation image sensors.  Notably, under the proposed framework, the two companies plan to form a joint venture (JV), with Sony serving as the majority and controlling shareholder. The JV is expected to build development and production lines at Sony’s newly constructed fab in Koshi City, Kumamoto Prefecture.  TSMC said that beyond manufacturing expansion, the partnership is also aimed at exploring emerging opportunities in physical AI applications, including automotive and robotics.  Through this collaboration, Sony will contribute its deep expertise in image sensor design, while TSMC will bring its advanced process technology and large-scale manufacturing capabilities. Both sides aim to combine their respective strengths to further enhance the performance and competitiveness of future image sensor technologies.  The move aligns with an April Reuters report, which noted that Japan’s Ministry of Economy, Trade and Industry (METI) has confirmed that the Japanese government will provide subsidies of up to ¥60 billion (approximately US$380 million) to Sony Semiconductor Solutions Corporation for the construction of an image sensor facility in Kumamoto Prefecture, western Japan.  Sony is a long-time customer of TSMC. As previously reported by Commercial Times, TSMC’s first Kumamoto fab—entering mass production in late 2024—supplies logic chips to Sony and DENSO, using 22/28nm and 12/16nm process technologies.  Separately, Sony has recently begun restructuring efforts, including a spin-off of its television business. Its CIS (image sensor) unit is also facing rising competitive pressure, as Samsung Electronics continues to expand its share in supplying image sensors for Apple, prompting Sony to seek new growth momentum in the segment, Commercial Times added.
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Release time:2026-05-09 10:16 reading:664 Continue reading>>

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