Few Surprises as Intel, GF Detail Process Technologies

　　Intel detailed plans to use cobalt for some interconnect layers at 10 nm, while Globalfoundries offered specifics on how it will utilize extreme ultraviolet (EUV) lithography for the first time at the 7-nm node in dueling process technology presentations at one of the most hotly anticipated sessions at the IEEE International Electron Device Meeting (IEDM) here.

　　Intel will use cobalt in on the bottom two layers of its 10-nm interconnect to get a five- to ten-fold improvement in electromigration and a two-fold reduction in via resistance. It represents the first time that a chip maker has detailed plans to introduce cobalt — a brittle metal long considered a promising dielectric candidate — in a process, according to G. Dan Hutcheson, chairman and CEO of VLSI Research.

　　Globalfoundries, which has said previously that it would insert EUV at the 7-nm node, detailed a platform that is entirely based on immersion optical lithography but is designed to enable the insertion of EUV for specific levels to improve cycle time and manufacturing efficiency. Gary Patton, Globalfoundries chief technology officer and senior vice president of global R&D, said in an interview with EE Times that kinks in EUV still need to be worked out — chiefly pellicle and inspection technologies — but that Globalfoundries is currently installing its first EUV production tools at its Fab 8 in upstate New York.

　　Hutcheson told EE Times that he was impressed overall with the presentations by Intel and Globalfoundries and added that hardcore technologists were disappointed with the lack of technical detail, typical for chipmakers that want to keep proprietary information close to the vest. "These guys don't give away anything," said Hutcheson.

　　But Hutcheson added that the improvements in logic transistor density that each company showed compared to its previous generation of process technology — above 2X — "show that the industry is still on pace with Moore's Law."

　　Both Intel and Globalfoundries had previously announced their newest process technologies. Intel's 10-nm node, first unveiled in March, features FinFETs with a 7-nm fin width at a 34-nm pitch and a 46-nm fin height made using self-aligned quadruple patterning (SAQP). Globalfoundries 7-nm node, first announced in September, uses SAQP to make fins and double patterning for metallization and boasts a 2.8-fold improvement in routed logic density and by up to 40% more performance or 55% lower power compared to its 14-nm process licensed from Samsung. Both processes support multiple voltage thresholds.

　　The use of cobalt by Intel for contact metallization at 10 nm could emerge as a differentiator in the advanced semiconductor manufacturing battleground. Globalfoundries at 7 nm continues to use the copper/low-k dielectrics that have been used by the semiconductor industry for the past several nodes.

　　In an interview with EE Times following the presentation, Patton and Basanth Jagannathan, a distinguished member of Globalfoundries' technical staff who presented the 7-nm process technology, said that sticking with copper/low-k provides reliability benefits, reducing complexity and yield risk.

　　"The copper system still has a lot of juice left in it," said Jagannathan.

　　Another clear difference between the process technologies presented is Globalfoundries' use of double-patterning for back-end metallization. In his presentation, Jagannathan argued that using SAQP offers density advantages but also severely hampers flexibility that customers depend on.

　　"This is a foundry technology," said Jagannathan. "It caters to all sorts of designs."

　　Patton told EE Times that sticking with double-patterning for the back end "doesn't mean we aren't dense. It's not just all about pitches. We get to the density target a little bit of a different way."

　　In the same advanced platform technologies in which the Intel 10-nm and Globalfoundries 7-nm technologies were presented, Intel also offered a separate paper on its 22-nm FinFET low-power technology that also captured Hutcheson's attention. This process — billed as ideal for mobile and RF applications — is illustrative of a new trend in which foundry vendors are going back and optimizing older process nodes, he said. "That really is a new trend," added Hutcheson.

　　Following the process technology session, Patton was one of three people to receive an IEEE Award. Patton, who said he first attended IEDM as a student 35 years ago, was recognized with the IEEE Frederik Philips Award, awarded for industry influence and leadership in the development of leading-edge microelectronics technology and collaborative research.